-- ***********************************************
-- *                                             *
-- Extraction du préambule et démultiplexage     *
-- *               CCIR601                       *
-- *  J. WEISS, septembre 2001                   *
-- *                                             *
-- * Entrée : Bus CCIR (8 bits, 27 MHz)          *  
-- * Traitement :                                *
-- *     Détection de l'En-Tête : FF 00 00 XY)   *
-- *     Démultiplexage du bus en Y, Cr, Cb      *
-- * Sorties :                                   *
-- *     3 bus 8 bits : Y, Cr, Cb                *
-- *     Signaux de synchro : F, V, H            *
-- *     Signaux de validation Luma/Chroma       *
-- ***********************************************


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY CCIR_DECODER IS

	PORT
	(
		BusE					: IN	UNSIGNED (7 DOWNTO 0);	-- Bus CCIR
		Y						: OUT	UNSIGNED (7 DOWNTO 0);	-- Bus Luminance
		Cr						: OUT	UNSIGNED (7 DOWNTO 0);	-- Bus Chrominance Rouge
		Cb						: OUT	UNSIGNED (7 DOWNTO 0);	-- Bus Chrominance Bleu
		CK27M					: IN	STD_LOGIC;				-- Horloge 27 MHz
		CCIR					: OUT	STD_LOGIC;				-- présence de XY
		PREFIX					: INOUT	STD_LOGIC;				-- présence de FF 00 00
		F						: OUT	STD_LOGIC;				-- Synchronisation (Frame)
		V						: OUT	STD_LOGIC;				-- Synchronisation (Vertical)
		H						: OUT	STD_LOGIC;				-- Synchronisation (Horizontal)
	    LUMA					: OUT	STD_LOGIC;				
	    Rouge					: OUT	STD_LOGIC				
	);
	
END CCIR_DECODER;

ARCHITECTURE a OF CCIR_DECODER IS

	SIGNAL	q		: INTEGER RANGE 0 to 3;
	SIGNAL	CCIR_Int: STD_LOGIC;
	SIGNAL	LUMA_Int: STD_LOGIC;
	SIGNAL	Rouge_Int: STD_LOGIC;
	SIGNAL	Butee_E_H	: STD_LOGIC;
	SIGNAL	Butee_E_L	: STD_LOGIC;
	SIGNAL	Butee_Int_H	: STD_LOGIC;
	SIGNAL	Butee_Int_L	: STD_LOGIC;

	SIGNAL	Y_Int	:UNSIGNED (7 DOWNTO 0);
	SIGNAL	Cr_Int	:UNSIGNED (7 DOWNTO 0);
	SIGNAL	Cb_Int	:UNSIGNED (7 DOWNTO 0);
	SIGNAL	Bus_Int	:UNSIGNED (7 DOWNTO 0);
	SIGNAL	Bus_Tmp	:UNSIGNED (7 DOWNTO 0);
BEGIN

-- Extraction des codes F, V et H (4ème octet du préambule)
	PROCESS (CK27M)
	BEGIN
		IF BusE = 255 THEN
			Butee_E_H <= '1';
		ELSE
			Butee_E_H <= '0';
		END IF;
		IF BusE = 0 THEN
			Butee_E_L <= '1';
		ELSE
			Butee_E_L <= '0';
		END IF;

		IF (CK27M'EVENT AND CK27M = '1') THEN
			Bus_Int <= BusE;
			Butee_Int_H <= Butee_E_H;
			Butee_Int_L <= Butee_E_L;
			IF Butee_Int_H = '1' or Butee_Int_L = '1' or Butee_E_H = '1' or Butee_E_L = '1' THEN
				Bus_Tmp <="10000000";
			ELSE
				Bus_Tmp <= BusE;
			END IF;

			CASE q is
			When 0 =>
				CCIR_Int <= '0';
				IF Butee_Int_H = '1' AND Butee_E_L = '1' THEN
					PREFIX <= '1';
					q <= q + 1;
				END IF;
			When  1 =>
				IF Butee_Int_L = '1' THEN
					PREFIX <= '1';
					q <= q + 1;
				ELSE
					PREFIX <= '0';
					q <= 0;
				END IF;
			When  2 =>
				IF Butee_Int_L = '1' THEN
					PREFIX <= '1';
					CCIR_Int <= '1';
					q <= q + 1;
				F <= BusE(6);
				V <= BusE(5);
				H <= BusE(4);

				ELSE
					PREFIX <= '0';
					q <= 0;
				END IF;

			When 3	=>
				CCIR_Int <= '0';
				PREFIX <= '0';
				--F <= Bus_Int(6);
				--V <= Bus_Int(5);
				--H <= Bus_Int(4);
				q <= 0;
			When others	=>
				PREFIX <= '0';
				CCIR_Int <= '0';
				q <= 0;
			END CASE;

		END IF;
	END PROCESS;

-- Génération de LUMA/ROUGE : LUMA (13,5 MHz) et Rouge (6,75 MHz)
	PROCESS (CK27M)
	BEGIN
		IF (CK27M'EVENT AND CK27M = '1') THEN
			IF CCIR_Int = '1' THEN
				LUMA_Int <= '0';
				Rouge_Int <= '0';
			ELSE
				LUMA_Int <= not(LUMA_Int);
				Rouge_Int <= LUMA_Int XOR Rouge_Int;
			END IF;
		END IF;
	END PROCESS;
	CCIR <= CCIR_Int;
	LUMA <= LUMA_Int;
	ROUGE <= Rouge_Int;

-- Démultiplexage du bus
	PROCESS (CK27M)
	BEGIN
		IF (CK27M'EVENT AND CK27M = '1') THEN
			If LUMA_Int = '1' THEN
				Y_Int <= Bus_Tmp;
			END IF;
			If LUMA_Int = '0' THEN
				IF Rouge_Int = '0' THEN
					Cb_Int <= Bus_Tmp;
				ELSE
					Cr_Int <= Bus_Tmp;
				END IF;
			END IF;
				Y <= Y_Int;
		END IF;
	END PROCESS;
	Cr <= Cr_Int;
	Cb <= Cb_Int;
END a;