
| Address | DLAB | Function | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | Reciever Buffer Register (Read Only) Transmitter Holding Register (Write Only) |
Data0 | Data1 | Data2 | Data3 | Data4 | Data5 | Data6 | Data7 |
| 1 | Divisor Latch (LSB) |
Bit0 | Bit1 | Bit2 | Bit3 | Bit4 | Bit5 | Bit6 | Bit7 | |
| 1 | 0 | Interrupt Enable Register |
Enable Recieved Data Available Interrupt |
Enable Transmitter Holding Register Empty Interrupt |
Enable Reciever Line Status Interupt |
Enable Modem Status Interrupt |
0 | 0 | 0 | 0 |
| 1 | Divisor Latch (MSB) |
Bit0 | Bit1 | Bit2 | Bit3 | Bit4 | Bit5 | Bit6 | Bit7 | |
| 2 | Interrupt ID Register |
"0" if Int. Pending |
Interrupt ID Bit (0) |
Interrupt ID Bit (1) |
0 | 0 | 0 | 0 | 0 | |
| 3 | Line Control Register |
Word Length Select Bit 0 |
Word Length Select Bit 1 |
Number of STOP Bits |
Parity Enable |
Even Parity Select |
Stick Parity | Set Break | Divisor Latch Access Bit DLAB |
|
| 4 | MODEM Control Register |
Data Terminal Ready (DTR) |
Request to Send (RTS) |
Out 1 | Out 2 | Loop | 0 | 0 | 0 | |
| 5 | Line Status Register |
Data Ready (DR) |
Overrun Error (OR) |
Parity Error (PE) |
Framing Error (FE) |
Break Interrupt (BI) |
Transmitter Holding Register Empty |
Transmitter Shift Register Empty |
0 | |
| 6 | MODEM Status Register |
Delta Clear to Send (DCTS) |
Delta Data Set Ready (DDSR) |
Trailing Edge Ring Ind. |
Delta Recieve Line Signal Detect |
Clear To Send (CTS) |
Data Set Ready (DSR) |
Ring Ind. (RI) |
Recieved Line Signal Detect |

| Desired Baud Rate | Divisor Used |
|---|---|
| 4,8 | 0x5DC0 |
| 5 | 0x5A00 |
| 50 | 0x0900 |
| 75 | 0x0600 |
| 150 | 0x0300 |
| 300 | 0x0180 |
| 600 | 0x00C0 |
| 1200 | 0x0060 |
| 2400 | 0x0030 |
| 4800 | 0x0018 |
| 9600 | 0x000C |
| 10400 | 0x000B |
| 19200 | 0x0006 |
| 38400 | 0x0003 |
| 56000 | 0x0002 |
