Registres de l'UART
8250


Address DLAB Function 0 1 2 3 4 5 6 7
0 0 Reciever Buffer
Register
(Read Only)

Transmitter
Holding Register
(Write Only)
Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7
1 Divisor Latch
(LSB)
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
1 0 Interrupt
Enable
Register
Enable
Recieved
Data
Available
Interrupt
Enable
Transmitter
Holding
Register
Empty
Interrupt
Enable
Reciever
Line
Status
Interupt
Enable
Modem
Status
Interrupt
0 0 0 0
1 Divisor Latch
(MSB)
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
2 Interrupt ID
Register
"0" if
Int. Pending
Interrupt ID
Bit (0)
Interrupt ID
Bit (1)
0 0 0 0 0
3 Line Control
Register
Word Length
Select Bit 0
Word Length
Select Bit 1
Number of
STOP Bits
Parity
Enable
Even Parity
Select
Stick Parity Set Break Divisor Latch
Access Bit
DLAB
4 MODEM Control
Register
Data Terminal
Ready (DTR)
Request to
Send (RTS)
Out 1 Out 2 Loop 0 0 0
5 Line Status
Register
Data Ready
(DR)
Overrun Error
(OR)
Parity Error
(PE)
Framing Error
(FE)
Break
Interrupt
(BI)
Transmitter
Holding
Register
Empty
Transmitter
Shift
Register
Empty
0
6 MODEM Status
Register
Delta Clear to
Send (DCTS)
Delta Data Set
Ready (DDSR)
Trailing Edge
Ring Ind.
Delta Recieve
Line Signal
Detect
Clear To
Send
(CTS)
Data Set
Ready
(DSR)
Ring Ind.
(RI)
Recieved Line
Signal Detect


Baud Rates using 1.8432 MHz Crystal :
Desired Baud Rate Divisor Used
4,80x5DC0
50x5A00
500x0900
750x0600
1500x0300
3000x0180
6000x00C0
12000x0060
24000x0030
48000x0018
96000x000C
104000x000B
192000x0006
384000x0003
560000x0002


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